谭思昊;李昱东;徐烨峰;闫江;

• 1:中国科学院微电子研究所

• 2:微电子器件与集成技术重点实验室

摘要(Abstract)：

随着CMOS技术发展到22nm技术节点以下,体硅平面器件达到等比例缩小的极限。全耗尽超薄绝缘体上硅CMOS(FDSOI)技术具有优秀的短沟道效应控制能力,利用TCAD软件,对不同埋氧层厚度的FDSOI器件短沟道效应进行数值仿真,研究减薄BOX厚度及器件背栅偏压对器件性能和短沟道效应的影响。仿真结果表明,减薄BOX厚度使FDSOI器件的性能和短沟道效应大幅提升,薄BOX衬底背栅偏压对FDSOI器件具有明显的阈值电压调制作用,6.00V的背栅偏压变化产生0.73V的阈值电压调制。在适当的背栅偏压下,FDSOI器件的短沟道特性(包括DIBL性能等)得到优化。实验结果表明,25nm厚BOX的FDSOI器件比145nm厚BOX的FDSOI器件关断电流减小近50%,DIBL减小近20%。

关键词(KeyWords)：FDSOI;超薄埋氧层;仿真研究;短沟道效应;背栅偏压

Abstract:

Keywords:

基金项目(Foundation):国家科技重大专项(2013ZX02303-001-001)

作者(Author):谭思昊;李昱东;徐烨峰;闫江;

Email:

参考文献(References)：

• [1]Cheng K,Khakifirooz A,Kulkarni P,et al.Extremely thin soi(ETSOI)technology:Past,present,and future[C]//Proceedings of the 2010IEEE International SOI Conference.San Diego,CA:IEEE,2010:1-4.

• [2]Faynot O,Andrieu F,Weber O,et al.Planar fully depleted SOI technology:A powerful architecture for the 20nm node and beyond[C]//Proceedings of the Electron Devices Meeting(IEDM)2010 IEEE International.San Fransisco,CA:IEEE,2010:3.2.1-3.2.4.

• [3]Brozek T.Micro-and nanoelectronics:Emerging device challenges and solutions[M].CRC Press,2014:218-221.

• [4]Ito M,Yamagata K,Miyabayashi H,et al.Scalability potential in Eltran(R)SOI-epi wafer[C]//Proceedings of the 2000IEEE International SOI Conference.Wakefield,MA:IEEE,2000:10-11.

• [5]Delprat D,Boedt F,David C,et al.SOI substrate readiness for 22/20nm and for fully depleted planar device architectures[C]//Proceedings of the 2009IEEE International SOI Conference.Foster city,CA:IEEE,2009:1-4.

• [6]Majumdar A,Wang X,Kumar A,et al.Gate length and performance scaling of undoped-body extremely thin SOI mosfets[J].Electron Device Letters,IEEE,2009,30(4):413-415.

• [7]Khakifirooz A,Cheng K,Reznicek A,et al.Scalability of extremely thin soi(ETSOI)MOSFETs to sub-20nm gate length[J].Electron Device Letters,IEEE,2012,33(2):149-151.

• [8]Feng Shuai,Zhao Lichuan,Zhang Qingzhu,et al.A simulation analysis of performance of both implanted doping and in situ doping ETSOI pMOSFETs[J].Journal of Semiconductors,2015,(4):184-188.

• [9]Fenouillet-Beranger C,Perreau P,Pham-Nguyen L,et al.Hybrid FDSOI/bulk high-K/metal gate platform for low power(lp)multimedia technology[C]//Proceedings of the 2009IEEE International Electron Devices Meeting(IEDM).Baltimore,MD:IEEE,2009:1-4.

• [10]Liu Q,Yagishita A,Loubet N,et al.Ultra-thin-body and box(UTBB)fully depleted(FD)device integration for 22nm node and beyond[C]//Proceedings of the 2010Symposium on VLSI Technology(VLSIT).Honolulu:IEEE,2010:61-62.

• [11]Liu Q,DeSalvo B,Morin P,et al.FDSOI CMOS devices featuring dual strained channel and thin box extendable to the 10nm node[C]//Proceedings of the 2014 IEEE International Electron Devices Meeting(IEDM).San Fransisco,CA:IEEE,2014:9.1.1-9.1.4.

• [12]Doris B,DeSalvo B,Cheng K,et al.Planar fully-depleted-silicon-on-insulator technologies:Toward the 28nm node and beyond[J].Solid-State Electronics,2016,117:37-59.

• [13]Tang Z Y,Tang B,Zhao L C,et al.Impacts of back gate bias stressing on device characteristics for extremely thin SOI(ETSOI)MOSFETs[J].Electron Device Letters,IEEE,2014,35(3):303-305.

• [14]Paolo G.International Technology Roadmap for Semiconductors 2014[DB/OL].http://www.itrs2.net/,2016.

• [15]冯帅.14/16nm ETSOI器件仿真与研制[D].贵州:贵州大学,2015.Feng Shuai.Simulation and fabrication of 14/16nm ETSOI devices[D].Guizhou:Guizhou University,2015.

• [16]Colinge J P.FinFETs and other multi-gate transistors[M].USA:Springer,2008:102-106.